Provisions of, e.g., PCI Bus Specification Revision 2.1 include a constraint that the order of write messages from input/output devices, serving as sources, arranged on a PCI bus must be ensured. In other words, it must be ensured that the preceding write message is processed and, after that, the following write message is processed.
FIG. 1 is a diagram showing the structure of a multiprocessor system for ensuring consistency of data in accordance with a directory method. The multiprocessor system includes a plurality of processor nodes 101-1, . . . , 101-i, and 101-m (i and m are integers of 2 or more), and a plurality of input/output nodes 103-1, . . . , 103-j, . . . 103-n (and n are integers of 2 or more). The processor nodes 101-1 to 101-m and the input/output nodes 103-1 to 103-n are connected to a network 102 and each of them is operated in response to a clock externally supplied. The processor node 101-1 includes processors 110-1-1 and 110-1-2, a directory 120-1, a main memory (memory) 130-1, and a memory controller 140-1. The other processor nodes have the same structure. Each main memory stores a plurality of data. Each data includes a value indicating descriptions of the data. On the other hand, the input/output node 103-1 includes an input/output controller 150-1 and a plurality of input/output devices 160-1-1 and 160-1-2, each device issuing a message in accordance with a command externally supplied. The other input/output nodes have the same structure. In the following description, an explanation may be made using reference numerals which are not shown in FIG. 1 for the sake of convenience. For example, although the processor node 101-2 is not shown in the diagram, it includes a main memory 130-2, a memory controller 140-2, and so forth.
A conventional art which satisfies the above-described constraint on the order of write messages in a multiprocessor system as shown in FIG. 1 will be described. Japanese Unexamined Patent Application Publication No. 2001-216259 (hereinafter, referred to as Patent Document 1) discloses a technique (hereinbelow, referred to as Related Art 1) which satisfies the order constraint by suspending issuing of a write message until the completion of the preceding write message is ensured, the technique being described in “Problems to be Solved by the Invention” in Patent Document 1.
The operation according to Related Art 1 in a case where write messages are successively issued on the order constraint will now be described with reference to FIGS. 1 and 2. FIG. 2 shows the operation in a case where the input/output device 160-1-1 issues write messages for data A, B, and C in steps 1, 2, and 3, respectively. It is assumed that the data A and the data B are originated (homed) at the processor node 101-1 and the data C is homed at the processor node 101-2 (not shown). One step corresponds to one clock.
In step 2, the input/output controller 150-1 receives a write A message, serving as a write message, from the input/output device 160-1-1. In step 3, the input/output controller 150-1 outputs an update A message, including a value specified in the write A message, through the network 102 to the home memory controller 140-1.
In step 4, the memory controller 140-1 updates the value included in the corresponding data stored in the main memory 130-1 to the value specified in the update A message in response to the update A message sent from the input/output controller 150-1. In step 5, the memory controller 140-1 outputs a complete A message through the network 102 to the input/output controller 150-1. In step 6, the input/output controller 150-1 receives the complete A message from the memory controller 140-1, thus recognizing that the preceding write A has been completed.
In addition, in step 3, the input/output controller 150-1 receives a write B message, serving as a second write message. In this instance, the input/output controller 150-1 suspends the write B message until the preceding write A is completed, i.e., step 6. In step 7, the input/output controller 150-1 outputs an update B message including a value designated in the write B message through the network 102 to the memory controller 140-1.
In step 8, the memory controller 140-1 updates the value in the corresponding data stored in the main memory 130-1 to the value designated in the update B message in response to the update B message sent from the input/output controller 150-1. In step 9, the memory controller 140-1 outputs a complete B message through the network 102 to the input/output controller 150-1. In step 10, the input/output controller 150-1 receives the complete B message from the memory controller 140-1, thus recognizing that the preceding write B has been completed.
In step 4, the input/output controller 150-1 also receives a write C message, serving as a third write message. In this case, the input/output controller 150-1 suspends the write C message until the preceding write A and write B are completed, i.e., step 10. In step 11, the input/output controller 150-1 outputs an update C message including a value designated in the write C message through the network 102 to the memory controller 140-2 (not shown).
In step 12, the memory controller 140-2 updates the value in the corresponding data stored in the main memory 130-2 (not shown) to the value specified in the update C message in response to the update C message sent from the input/output controller 150-1. In step 13, the memory controller 140-2 outputs a complete C message through the network 102 to the input/output controller 150-1. In step 14, the input/output controller 150-1 receives the complete C message from the memory controller 140-2, thus recognizing that the write C has been completed.
As described above, the input/output controller 150-1 issues a write message after the preceding write message is completed, so that the order of a plurality of write messages issued by the input/output devices 160-1-1 and 160-1-2 can be ensured. However, processing three write messages requires 14 steps. The same applies to the other input/output controllers.
Patent Document 1 also discloses a technique (hereinafter, referred to as Related Art 2) for solving such a problem that processing time for write messages is long. The problem results in a degradation in performance. Related Art 2 permits the issuing of successive write messages addressed to the same processor node, i.e., the issuing of the following messages before the completion of the preceding message is ensured.
The operation according to Related Art 2 will now be described with reference to FIGS. 1 and 3.
In step 2, the input/output controller 150-1 receives a write A message, serving as a first write message, and recognizes that the write A message relates to the write operation for updating data homed at the processor node 101-1 (memory controller 140-1). In step 3, the input/output controller 150-1 outputs an update A message including a value specified in the write A message through the network 102 to the home memory controller 140-1.
In step 4, the memory controller 140-1 updates the corresponding data stored in the main memory 130-1 in response to the update A message sent from the input/output controller 150-1. In step 5, the memory controller 140-1 outputs a complete A message through the network 102 to the input/output controller 150-1. In step 6, the input/output controller 150-1 receives the complete A message from the memory controller 140-1 and recognizes that the preceding write operation A has been completed.
In step 3, the input/output controller 150-1 also receives a write B message, serving as a second write message. The input/output controller 150-1 recognizes that the write B message relates to the write operation for updating other data homed at the processor node 101-1 (memory controller 140-1), i.e., recognizes that the target data of the current message is originated from the same home as that associated with the preceding write A message. In this case, in step 4, the input/output controller 150-1 outputs an update B message including a value specified in the write B message through the network 102 to the home memory controller 140-1 without waiting the completion of the write A.
In step 5, in response to the update B message sent from the input/output controller 150-1, the memory controller 140-1 updates the corresponding data stored in the main memory 130-1. In step 6, the memory controller 140-1 outputs a complete B message through the network 102 to the input/output controller 150-1. In step 7, the input/output controller 150-1 receives the complete B message from the memory controller 140-1.
In step 4, the input/output controller 150-1 further receives a write C message, serving as a third write message. The input/output controller 150-1 recognizes that the write C message relates to the write operation for updating data homed at the processor node 101-2 (memory controller 140-2), which are not shown in the diagram, and also recognizes that the target data of the current message is originated from the home node different from that associated with the preceding write A message and write B message. In this case, the input/output controller 150-1 suspends the write C message until step 7 in which both of the write messages (write A message, write B message) are completed. In step 8, the input/output controller 150-1 outputs an update C message including a value designated in the write C message through the network 102 to the memory controller 140-2.
In step 9, in response to the update C message sent from the input/output controller 150-1, the memory controller 140-2 updates the corresponding data unit stored in the main memory 130-2. In step 10, the memory controller 140-2 outputs a complete C message through the network 102 to the input/output controller 150-1. In step 11, the input/output controller 150-1 receives the complete C message from the memory controller 140-1 and recognizes that the write C has been completed.
As described above, the input/output controller 150-1 successively issues write messages associated with the same home and then issues a write message associated to another home after the preceding write messages are completed. The network 102 ensures the order of messages between two points. Accordingly, in the above-described example, it is ensured that the write A message and the write B message reach the memory controller 140-1 in this order. Therefore, the memory controller 140-1 does not process the write B message before processing the write A message. The order of these messages can be ensured.
In Related Art 2, however, processing three write messages requires 11 steps.
In Related Arts 1 and 2, each input/output controller cannot successively process a plurality of write messages, supplied from the corresponding input/output devices, addressed to different processor nodes. Disadvantageously, it takes long time to process the write messages through the input/output controller.
It is an object of the present invention to provide a multiprocessor system capable of successively processing a plurality of write messages, supplied from input/output devices, addressed to different processor nodes.
Another object of the present invention is to provide a multiprocessor system capable of reducing the time required to process write messages through each input/output controller.